1. Field of the Invention
The present invention relates to an internal voltage generating circuit for generating an internal voltage of a level between the levels of an external supply voltage and a ground voltage. Specifically, the present invention relates to an internal voltage generating circuit for generating a temperature-independent internal voltage. More specifically, the invention relates to a configuration of a circuit for generating an internal voltage determining a voltage level of data stored in a memory cell in a semiconductor memory device.
2. Description of the Background Art
With recent developments of computers and information processing terminals, requirements are becoming severer for memories employed as main memories in these devices and equipment. Specifically, in addition to a large storage capacity, speed-up of an effective data transfer rate as well as reduction of power consumption are strongly required for application to portable equipment. To consider, as an example, DRAMs (Dynamic Random Access Memories) used most widely as main memory devices, DRAMs capable of transferring data at a high clock rate, such as an SDRAM (Synchronous DRAM) inputting/outputting data synchronously with a clock signal and a DDR (Double Data Rate) SDRAM inputting/outputting data synchronously with both of the rising and falling edges of a clock signal, are coming into wide use.
In a DRAM, information is stored in the form of charges in a capacitor of a memory cell. If data of H (high) level written in a DRAM cell is left as it is, the data would be lost in the course of time due to a leakage current. Therefore, a periodic restoring operation called refresh is required in DRAMs.
For recent DRAMs, an operation referred to as self refresh is defined by specifications. In this self refresh operation mode, an internal timer provided in a DRAM automatically sets a refresh timing, and the refresh operation is automatically carried out according to this refresh timing. The self refresh operation is performed in a standby period in which no access is made to the DRAM. Accordingly, reduction of a self refresh current consumed in the refresh operation can decrease current consumption of the DRAM and thus extend the life of a battery in a battery-driven information communication terminal of a portable type, for example, thereby to lengthen a continuous standing-by time.
In order to reduce the self refresh current, data holding characteristics of a memory cell should be improved to extend an interval Tsrc between refresh operations. In terms of manufacturing process, the improvement is accomplished by: (1) using a material of a high dielectric constant as an insulating film for a memory cell capacitor or devising a shape of the memory cell capacitor for increasing the capacitance value of the memory cell capacitor, and (2) reducing an off-leakage (subthreshold leakage) current Ilb of a memory cell transistor and a leakage current Ils in a PN junction between a memory cell capacitor electrode and a semiconductor substrate.
In terms of circuit design, the data holding characteristics of the memory cell can be improved by devising a power supply arrangement in a memory cell array. As one of approaches for improvement in terms of the circuit design, a BSG (Boosted Sense ground) scheme is proposed by Asakura et al. Details of the BSG scheme are described, for example, in IEEE Journal of Solid-State Circuits, 1994, pp. 1303-1309. A brief description is given below of principles of the BSG scheme.
FIG. 16 schematically shows a cross sectional structure of a memory cell of a conventional DRAM. In FIG. 16, the memory cell includes high-concentration N type impurity regions 502a and 502b formed at a surface of a semiconductor substrate 500 with an interval therebetween, a conductive layer 504 formed on the channel region between impurity regions 502a and 502b with a gate insulating film 503 underlaid, and a conductive layer 505 connected electrically to impurity region 502a. On these conductive layers 504 and 505, interlayer insulating films 506a and 506b of a double layer structure are formed. Conductive layers 504 and 505 provide a word line WL and a bit line BL, respectively.
The memory cell further includes a conductive layer 510 connected electrically to impurity region 502b via a contact hole formed in interlayer insulating films 506a and 506b, and a conductive layer 514 arranged facing to the top of conductive layer 510. Conductive layer 510 is formed having a V-shaped cross section, and conductive layer 514 includes a protrusion 514a extending into the V-shaped region at the upper region of conductive layer 510 with a capacitor insulating film 512 interposed therebetween. Conductive layer 510 functions as a connection node between an access transistor and a memory cell capacitor of the memory cell, i.e., a storage node SN. The memory cell capacitor Cs is formed in the region where conductive layers 510 and 514 face each other via capacitor insulating film 512.
It is assumed that, in the memory cell shown in FIG. 16, word line WL is maintained at a ground voltage GND level, a bit line voltage Vbl is applied to bit line BL, and a voltage Vch corresponding to H level data is held on storage node SN. A cell plate voltage Vcp (a voltage between the voltages corresponding to H level data and L level data) is applied to conductive layer 514 serving as a cell plate electrode layer CP.
Main leakage sources in the memory cell are: (1) a substrate leakage current Ils flowing to P type substrate 500 via the PN junction between impurity region 502b and P type substrate 500 in memory cell capacitor Cs, and (2) a leakage current Ilb flowing toward bit line BL that is determined by subthreshold characteristics of the access transistor.
The magnitude of leakage current Ils to P type substrate 500 depends on a potential difference Vpn applied across the PN junction between impurity region 502b and P type substrate 500. A greater potential differential Vpn increases leakage current Ils. In FIG. 16, the voltage on storage node SN is voltage Vch corresponding to H level data and a bias voltage Vbb is applied to P type substrate 500. Accordingly, the potential difference Vpn is represented by the following expression.
Vpn=Vchxe2x88x92Vbb 
Leakage current Ilb flowing toward bit line BL via the access transistor is represented by the following expression using a difference between a gate-source voltage Vgs of the access transistor and a threshold voltage Vth.
Ilb=Ilb0xc2x710{circumflex over ( )}[(Vgsxe2x88x92Vth)/S]xe2x80x83xe2x80x83(1) 
Here, xe2x80x9cxe2x80x9d represents power. In expression (1), Ilb0 represents a current value defining threshold voltage Vth, and S is a coefficient determined by the transistor structure and the process and is represented by dVgs/dlogId. Here, Id represents a drain current. Expression (1) indicates that the bit line leakage current Ilb is strongly dependent on a gate-source voltage of an access transistor MT. The value of the leakage current Ilb becomes worst when the bit line is at L level. In a conventional case, the L level is equal to ground voltage GND level.
It seems from expression (1) that leakage current Ilb is independent of voltage Vbl of bit line BL connected to the access transistor. However, threshold voltage Vth depends on a substrate-source voltage Vbs=Vbbxe2x88x92Vbl. If bias voltage Vbb is a non-positive voltage and the bit line voltage or source voltage Vbl is lower, the absolute value of substrate-source voltage Vbs is smaller and threshold voltage Vth is also smaller.
For example, in a memory block to be refreshed, if a memory cell among the memory cells connected to a non-selected word line has an associated bit line swung to a voltage corresponding to L level data, an access transistor of the memory cell connected to the non-selected word line has substrate-source voltage Vbs smaller in absolute value, and bit line leakage current Ilb increases even if the non-selected word line WL has ground voltage GND level. As understood from the above expression (1), even if threshold voltage Vth slightly deviates by merely 0.1 V, bit line leakage current Ilb varies about tenfold since generally S factor is of the order of 0.1 V.
In order to reduce bit line leakage current Ilb, it can be considered that bias voltage Vbb of P type substrate 500 is made negative as shown in FIG. 17A. By setting substrate bias voltage Vbb at a value which is great in the negative direction, the absolute value of substrate-source voltage Vbs can be increased. Accordingly, threshold voltage Vth of the memory cell access transistor MT can be increased to reduce bit line leakage current Ilb.
However, voltage difference Vpn (=Vchxe2x88x92Vbb) applied across the PN junction between impurity region 502b and P type substrate 500 increases and accordingly substrate leakage current Ils increases. A sense supply voltage Vdds determines the voltage level of voltage Vch corresponding to H level data on storage node SN. If substrate leakage current Ils increases because of this deeper negative substrate bias, when sense supply voltage Vdds is decreased, it is difficult to hold H level data over a long period of time.
According to the BSG scheme, in order to simultaneously reduce both of the bit line leakage current Ilb and substrate leakage current Ils, a voltage of L level data or sense ground voltage is set at a voltage Vbsg slightly higher than ground voltage GND as shown in FIG. 17B. A bias voltage to the P type substrate (backgate of access transistor) is set at ground voltage GND level. Word line WL is at ground voltage GND level when it is not selected. Gate-source voltage Vgs of access transistor MT is thus a negative voltage, xe2x88x92Vbsg. Therefore, from expression (1), it is clear that bit line leakage current Ilb exponentially decreases in BSG scheme. As ground voltage GND is applied to the P type substrate (backgate), voltage difference Vpn applied across the PN junction between impurity region 502b and P type substrate 500 corresponding to storage node SN is equal to voltage Vch of H level data. The voltage difference applied across the PN junction can be made smaller and accordingly substrate leakage current Ils can be reduced.
In other words, gate-source voltage Vgs of access transistor MT can be set at a negative value without applying a negative voltage to P type substrate 500. In addition, voltage Vbs applied across the PN junction between source impurity region 502a of access transistor MT and P type substrate 500 is in a reverse-bias state. Thus, both of bit line leakage current Ilb and substrate leakage current Ils can be reduced. This reduction of the leakage currents improves charge holding characteristics of the memory cell and thus refresh interval Tsrc can be lengthened to reduce the refresh current.
The BSG scheme is highly effective on the improvement of refresh characteristics. However, if the BSG scheme is actually employed, the most important issue is generation and retention of a stable boosted sense ground voltage Vbsg. Not only the accuracy in level of boosted sense ground voltage Vbsg generated in a sense operation, but also the holding of the voltage level of boosted sense ground voltage Vbsg in the period during which a sense amplifier circuit is activated, are required. As discussed above, threshold voltage Vth of the access transistor is determined by voltage Vbs=Vbbxe2x88x92Vbl and bit line leakage current Ilb is determined according to the above expression (1). If bit line voltage Vbl decreases due to leakage and the like, bit line leakage current Ilb is increased and accordingly data retention characteristics of a memory cell would deteriorate.
A circuit for holding the level of boosted sense ground voltage Vbsg is already disclosed specifically by the inventor of the present invention in, 1999 Symposium on VLSI Circuits Digests of Technical Papers, xe2x80x9cA Precharged-Capacitor-Assisted Sensing (PCAS) Scheme with Novel Level Controller for Low Power DRAMsxe2x80x9d, T. Kono et al., pp. 123-124.
FIG. 18A shows a structure of a boosted sense ground voltage generating circuit shown in the reference mentioned above. Referring to FIG. 18A, the boosted sense ground voltage generating circuit 1 includes a reference voltage generating circuit 2 generating a reference voltage Vrfb, a level shift circuit 3 receiving reference voltage Vrfb from reference voltage generating circuit 2 and shifting the level thereof to generate a control voltage Vdt (=Vrfb+Vthp), an N channel MOS transistor 5 detecting a difference between control voltage Vdt from level shift circuit 3 and a voltage Vbsg on a low level sense supply line LPL to flow a current Ipg according to the detected voltage difference, a capacitance element 6 with its charging voltage adjusted by discharging current Ipg of difference detection MOS transistor 5, a precharge circuit 7 precharging capacitance element 6 to a predetermined voltage, a charge holding circuit 8 for holding charges stored in capacitance element 6, and a current drive circuit 9 according to charged voltage Vpg of capacitance element 6 to supply a current from an external supply node to low level sense supply line LPL.
Reference voltage generating circuit 2 includes variable resistance elements R1 and R2 connected in series between a node receiving an internal reference voltage (e.g. array supply voltage) Vdd0 which is independent of an external supply voltage and a ground node. Reference voltage Vrfb is output from the connection node connecting variable resistance elements R1 and R2.
Level shift circuit 3 includes a resistance element R3 and a P channel MOS transistor 3p connected in series between the internal power supply node and the ground node. Resistance element R3 has its resistance value set sufficiently higher than a channel resistance (ON resistance) of P channel MOS transistor 3p. Therefore, P channel MOS transistor 3p receives, at its gate, reference voltage Vrfb to operate in a source-follower mode and keep its source-gate voltage at the voltage level of the absolute value Vthp of the threshold voltage thereof. Level shift circuit 3 is merely required to charge the gate capacitance of difference detection MOS transistor 5 and the resistance value of resistance element R3 is increased to accordingly reduce current consumption.
MOS transistor 5 has its gate connected to an output node of level shift circuit 3 and its source connected to low level sense supply line LPL. When the difference between control voltage Vdt from level shift circuit 3 and voltage Vbsg on low level sense supply line LPL becomes greater than a threshold voltage Vthn, MOS transistor 5 is turned on to cause current Ipg to flow. A stabilization capacitance 10 for stabilizing gate voltage (control voltage) Vdt of MOS transistor 5 is provided at the gate of MOS transistor 5.
Precharge circuit 7 includes P channel MOS transistors 7a and 7b connected in series between an external supply node receiving an external supply voltage extVdd and a node 7d, and an N channel MOS transistor 7c connected between node 7d and MOS transistor 5. MOS transistors 7a and 7c receive, at the respective gates, a precharge instruction signal ZPRE and are turned on complementarily to each other. P channel MOS transistor 7b has its gate and drain connected to node 7d, operates in a diode mode, and causes voltage drop corresponding to the absolute value of the threshold voltage thereof.
Charge holding circuit 8 includes an inverter 8a inverting a charge transfer instruction signal CT, and a transmission gate 8b rendered conductive according to charge transfer instruction signal CT and an output signal of inverter 8a to selectively connect nodes 11 and 7d. When transmission gate 8b is non-conductive, capacitance element 6 is isolated from precharge circuit 7 and MOS transistor 5. Then, the charging and discharging path of capacitance element 6 is cut off and accordingly charges stored in capacitance element 6 are secured.
Boosted sense ground voltage generating circuit 1 further includes P channel MOS transistors 12a and 12b connected between the external supply node and a node 11. MOS transistor 12a receives, at its gate, a sense operation activation signal SE, and MOS transistor 12b has its gate connected to node 11 and operates in the diode mode. Sense operation activation signal SE is provided for activating an operation of a sense amplifier circuit 15 which operates using voltage Vbsg on low level sense supply line LPL as one operating supply voltage.
Sense amplifier circuit 15 starts its sensing operation according to sense operation activation signal SE in an active state of H level to supply a discharging current from a low level bit line to low level sense supply line LPL. A stabilization capacitance 16 for stabilizing boosted sense ground voltage Vbsg is provided to low level sense supply line LPL. An operation of the boosted sense ground voltage generating circuit shown in FIG. 18A is now described in conjunction with the operation waveforms illustrated in FIG. 18B.
Before time T0, sense operation activation signal SE is in the inactive state of L level and sense amplifier circuit 15 does not operate. In this state, MOS transistor 12a is turned on and node 11 is precharged to the voltage level of extVddxe2x88x92Vthp. Voltage Vpg on node 11 causes P channel MOS transistor 9a included in current drive circuit 9 to have its gate-source voltage equal to its threshold voltage and stay in substantially off state. Here, the P channel MOS transistors have the same threshold voltages. If there is any leakage path between low level sense supply line LPL and a node of ground voltage GND, for example, the voltage level of boosted sense ground voltage Vbsg gradually decreases.
When sense operation activation signal SE is in the inactive state, precharge instruction signal ZPRE is in the active state of L level. Accordingly, in precharge circuit 7, MOS transistor 7a is turned on, MOS transistor 7c is turned off, and node 7d is precharged to the voltage level of extVddxe2x88x92Vthp. Charge transfer instruction signal CT is at H level, transmission gate 8b is rendered conductive, and node 11 is precharged to the voltage level of extVddxe2x88x92Vthp by precharge circuit 7. These signals ZPRE and CT are periodically activated according to activation of sense operation activation signal SE.
At the time T0, sense operation activation signal SE is driven into the active state of H level and accordingly sense amplifier circuit 15 operates to supply a discharging current to low level sense supply line LPL. Here, suppose that boosted sense ground voltage Vbsg is at a voltage level lower than reference voltage Vrfb. MOS transistor 12a is turned off in response to activation of sense operation activation signal SE and precharging operation on node 11 is completed.
At time T1, precharge instruction signal ZPRE rises to H level, MOS transistor 7a is turned off, MOS transistor 7c is turned on, and accordingly precharging operation for capacitance element 6 by precharge circuit 7 is completed. At this time, MOS transistor 12a is turned off. Node 11 is thus isolated from the external supply node.
Difference detection MOS transistor 5 is coupled to capacitance element 6 via MOS transistor 7c and transmission gate 8b. MOS transistor 5 receives, at its gate, control voltage Vdt (=Vrfb+Vthp) and at its source, boosted sense ground voltage Vbsg. Then, MOS transistor 5 is turned on when the following expression (2) is satisfied to supply current from capacitance element 6 to low level sense supply line LPL.
Vrfb+Vthp greater than Vbsg+Vthn xe2x80x83xe2x80x83(2) 
If threshold voltages Vthp and Vthn are equal to each other, the voltage level of boosted sense ground voltage Vbsg is controlled such that the voltage level thereof is equal to reference voltage Vrfb. Here, the absolute value Vthp of the threshold voltage is simply referred to as threshold voltage. If threshold voltages Vthp and Vthn are not equal to each other, it may suffice that reference voltage Vrfb is set at Vbsg+Vthnxe2x88x92Vthp.
Charges stored in capacitance element 6 are discharged via MOS transistor 5 to low level sense supply line LPL. Specifically, MOS transistor 5 discharges current according to the difference between control voltage Vdt on node 3a and boosted sense ground voltage Vbsg on low level sense supply line LPL. This discharged current changes charged voltage Vpg of capacitance element 6. Capacitance element 6 has a capacitance value Cpg which is sufficiently smaller than capacitance value Cdl of stabilization capacitance 16. The current discharged by MOS transistor 5 significantly changes the charged voltage Vpg of capacitance element 6.
At time T2, charge transfer instruction signal CT falls to L level and transmission gate 8b becomes non-conductive. At time Txe2x80x2 between time T2 and time T1, the total charge Qpg represented by the following expression (3) flows to low level sense supply line LPL via MOS transistor 5.
Qpg=∫Ipgxc2x7dT xe2x80x83xe2x80x83(3) 
Here, integration period T satisfies the relation T1 less than T less than Txe2x80x2xe2x89xa6T2.
The voltage level of voltage Vpg on node 11 at time Txe2x80x2 is represented by the following expression (4).
Vpg=extVddxe2x88x92Vthpxe2x88x92Qpg/(Cpg+Cg) xe2x80x83xe2x80x83(4) 
Here, Cg represents a gate capacitance of MOS transistor 9a when MOS transistor 9a for drive is turned on and accordingly a channel is formed therein. In this current drive circuit 9, MOS transistor 9a is turned on when gate-source voltage Vgs becomes equal to the threshold voltage thereof. Specifically, when the following expression (5) is satisfied, MOS transistor 9a is turned on.
Vpg less than extVddxe2x88x92Vthp xe2x80x83xe2x80x83(5) 
It would be understood from the above expressions (4) and (5) that, when discharging occurs via MOS transistor 5, MOS transistor 9a for drive is immediately turned on to supply current from the external supply node to low level sense supply line LPL.
It is also understood from above expression (4) that a smaller capacitance value (Cpg+Cg) of node 11 considerably varies voltage Vpg on node 11 even if the amount of discharged charges Qpg is small. In other words, even if boosted sense ground voltage Vbsg slightly deviates from reference voltage Vrfb, discharged current Ipg via MOS transistor 5 significantly changes the voltage Vpg on node 11. Responsively, current immediately flows via drive MOS transistor 9a from the external supply node to low level sense ground line LPL to cause the voltage level of voltage Vbsg to rise.
At time T2, charge transfer instruction signal CT enters the inactive state of L level, transmission gate 8b becomes non-conductive, capacitance element 6 and MOS transistor 5 are isolated from each other, and voltage Vpg on node 11 is maintained at the voltage level attained at time T2. In this state, driving MOS transistor 9a supplies current to low level sense ground line LPL.
At time T3, precharge instruction signal ZPRE becomes active, charge transfer instruction signal CT becomes active, MOS transistor 5 is isolated from capacitance element 6, node 11 is precharged again to the voltage level extVddxe2x88x92Vthp by precharge circuit 7, and accordingly, preparation is made for the subsequent voltage difference detecting operation. This operation is repeatedly performed in the period during which sense operation activation signal SE is at H level. Boosted sense ground voltage Vbsg is controlled to be equal to reference voltage Vrfb.
As discussed above, with charged voltage at the capacitance element set according to the difference between voltage Vbsg on low level sense supply line LPL and control voltage Vdt, the voltage difference can be detected with reduced current consumption to speedily suppress the variation in level of boosted sense ground voltage Vbsg.
The voltage level of boosted sense ground voltage Vbsg is lower than control voltage Vdt by threshold voltage Vthn of MOS transistor 5 for difference detection. Generally, reference voltage Vrfb is set to meet the following relation, where a target value of boosted sense ground voltage Vbsg is Vbsg (0).
Vrfb=Vbsg(0)+Vthnxe2x88x92Vthp xe2x80x83xe2x80x83(6) 
If threshold voltages Vthn and Vthp have the same temperature characteristics and the value of (Vthnxe2x88x92Vthp) is always constant, reference voltage Vrfb is independent of temperature and has a constant value over a wide temperature range. The boosted sense ground voltage can thus be maintained at a constant value over a wide temperature range. However, there arise problems that values of threshold voltages Vthn and Vthp vary due to variation of process parameters and accordingly they have different temperature characteristics. Consequently, it is difficult to maintain reference voltage Vrfb at a constant value over a wide temperature range and eliminate dependency on an operation environment such as temperature-dependency of boosted sense ground voltage Vbsg.
As a resistance element employed in reference voltage generating circuit 2, a pure resistance element such as line resistance is desirably used for avoiding the temperature dependency of reference voltage Vrfb as much as possible. However, use of such a pure resistance element causes a problem of increase in the layout area.
Not only generation of the boosted sense ground voltage, but generation of sense power supply voltage Vdds with the similar structure to that of the circuit shown in FIG. 18A accompany similar problems. Specifically, a problem generally occurs in an internal voltage generating circuit employing a scheme of controlling charges stored in a capacitor according to a difference between a target voltage and a reference voltage, the problem being the difficulty in eliminating temperature-dependency of the target voltage.
In the transition period immediately after the power is on, the control voltage cannot be set at a predetermined voltage level until reference voltage Vdd0 (voltage generated internally and not depending on the external supply voltage) becomes stable. Consequently, a problem arises that an internal voltage such as the boosted sense ground voltage cannot be set at a desired level in a short period of time.
Further, in view of application to portable equipment and the like, it is desired that a required internal voltage is generated with current consumption and occupied area as small as possible.
An object of the present invention is to provide an internal voltage generating circuit capable of generating an internal voltage of a desired voltage level in a stable manner over a wide operation range.
Another object of the invention is to provide an internal voltage generating circuit capable of generating an internal voltage kept at a constant voltage level over a wide range of temperature.
Still another object of the invention is to provide an internal voltage generating circuit capable of speedily setting an internal voltage at a desired voltage level in a transition period such as a period immediately after power is on.
A further object of the invention is to provide an internal voltage generating circuit capable of generating an internal voltage of a desired voltage level without increasing current consumption and the area occupied thereby.
An internal voltage generating circuit according to one aspect of the invention includes a reference voltage generating circuit for generating a reference voltage, a comparator for comparing the reference voltage with a voltage on a first node to generate a signal indicating a result of the comparison, a current drive transistor coupled to a first power supply node to flow a current between the second node and the first power supply node according to an output signal of the comparator, and an output circuit coupled between the current drive transistor and a second power supply node to convert the current from the current drive transistor into a voltage and generate the voltage on a second node. The output circuit includes a voltage drop element causing voltage drop of a predetermined value between the second node and the first node.
The internal voltage generating circuit according to one aspect of the invention further includes a voltage compensation circuit according to a difference between a voltage on an internal voltage line and the voltage on the second node to cause a current flow between the internal voltage line and a third power supply node.
An internal voltage generating circuit according to another aspect of the invention includes first and second capacitance elements, a precharge circuit responsive to a clock signal for storing charges of opposite polarities respectively in the first and second capacitance elements, and an equalize circuit responsive to the clock signal to become conductive complementarily to the precharge circuit and electrically connect the first and second capacitance elements to an output node. A reference voltage is generated on the output node.
An internal voltage generating circuit according to still another aspect of the invention includes a difference detection transistor generating a current according to a difference between a reference voltage and a voltage on an internal voltage line, a capacitance element with a charged voltage determined by the current generated by the difference detection transistor, a current drive transistor according to the charged voltage of the capacitance element to cause current flow between the internal voltage line and a power supply node, and a reference voltage generating circuit for generating the reference voltage. The reference voltage generating circuit generates the reference voltage to cancel temperature dependency exhibited by the voltage on the internal voltage line through the difference detection transistor.
The comparison circuit is used to drive the current drive transistor in order to generate a voltage at a level substantially equal to the reference voltage and further generate a voltage difference on this voltage for comparison with an internal voltage to adjust the level of the internal voltage. In this way, the internal voltage can be generated according to the reference voltage. Use of the voltage drop element can eliminate temperature dependency of a voltage detected when a voltage difference is detected in the voltage compensation circuit.
The reference voltage is generated using the capacitance element and accordingly the reference voltage can be generated with a small occupying area and a small current consumption.
Further, if the reference voltage is generated using the capacitance element, the period of the charging/discharging operation of the capacitance element can be shortened in a transition period to stabilize the reference voltage speedily.
In addition, for the structure in which a voltage difference is detected by means of current and this current is converted into voltage to correct the voltage level of an internal voltage, the reference voltage can be generated so as to cancel temperature dependency exhibited by the internal voltage through the difference detecting current drive transistor, and accordingly the internal voltage having a constant voltage level over a wide temperature range can be generated.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.